Open and short tests are required for manufacturing high density printed circuit boards and ceramic substrates. In view of the high density in which electronic components are packaged onto each circuit board, the integrity of each circuit board, i.e. the integrity of the different metal interconnections that effect each of the net in the circuit boards, is of paramount import. Thus, defects such as an "open" circuit condition whereby higher than expected resistance appears between certain sections of a given network, or a "short" circuit condition whereby two separate networks, which theoretically should have infinite resistance therebetween, in fact appear to be shorted together, or have an unacceptable internet (leakage) resistance, are to be detected and avoided.
Testing of electrical interconnection networks for opens and shorts in networks results in improved product reliability. Typically, testing is done with a "bed-of-nails" test fixture. The nails are probes typically spaced 0.100 inches apart which make contact electrically between the tester and the points of contact on the board being tested. In the bed of nails method, it is highly desirable to contact all test points at once to avoid step and repeat operations. The difficulty with the bed-of-nails approach are problems with the probe heads which present design, manufacture, and maintenance; challenges and particularly with the decreasing size of surface features and grid spacings on boards being produced. Construction of a bed-of-nails test head for each of the different types of boards and substrates to be checked involves a high cost and long fabrication time.
An alternative to the bed-of-nails approach for testing for opens and shorts is using movable probes to measure the net capacitance relative to an internal or external reference plane. In so doing, an AC frequency based impedance measurement may be taken at selected nodes or networks relative to a reference. An exemplary prior art method in which two moving probes are used to perform tests on nets is disclosed in U.S. Pat. No. 4,565,966 to Burr et al. As disclosed, Burr performs a series of one point measurements of the capacitance of a network relative to a reference plane. To test the continuity of each net, a resistance measurement is effected between two probes, each placed at an end point of the net. This method, however, requires a capacitance data file which is established in a "learn" procedure wherein capacitance measurements are made for a series or set of circuit boards until enough data to establish "norm" values having statistical properties such as standard deviation. Moreover, the method of U.S. Pat. No. 4,565,966 uses an AC frequency based impedance measurement which requires a number of periods to compute.
Another alternative to the bed-of-nails approach for testing for opens and shorts is to apply a charge between a node on a network and a reference plane, to detect the presence or absence of a charge at subsequent nodes during a test sequence, and to compare the detected charge with a reference pattern of charge transfer.
In U.S. Pat. No. 5,138,266 a method is disclosed for testing circuit boards using a stored charge technique for identifying opens and shorts with a single probe. A probe is used to make contact with various nodes on the circuit board and to charge or discharge these nodes. A reference plane is closely spaced from the board under test, and a charge transfer measurement arrangement is connected to the reference plane. The charging of the nodes by capacitively coupling to the reference plane is measured and compared with a reference data file, thereby eliminating the need to develop a capacitance value data file. That is, the reference data file indicates whether the presence or absence of a charge for a particular node during the test sequence should be interpreted as a potential defect. A practical limitation of this method is that relatively small nets are unable to store appreciable charge. As a result, an accurate determination of whether a short exists between the charged net and another net cannot be made. Moreover, another limitation of this method is that resistive faults in the network paths may not be detected and, therefore, not providing complete test results suitable for assuring electrical integrity of the circuit board being tested.
Another exemplary prior art method for testing circuit boards using a stored charge technique in U.S. Pat. No. 5,122,753. A method for testing circuit boards is disclosed which uses an electron beam to charge networks within the circuit board to be tested. The method is one in which a first pass and second pass are available in order to determine whether a defect exists and to identify all faulty networks. The method is limited in its testing of opens in that it is unable to discriminate between the magnitude of potential opens, for example between 10 ohms and 10 megohms. Moreover, the electron beam has associated therewith a high cost of implementation.